1. Field of the Invention
The present invention relates to processes for the formation of metal salicide layers during semiconductor device fabrication and, in particular, to such a process that includes a step of depositing a metal layer by ion metal plasma deposition and that provides for a reduced risk of metal silicide bridging defects.
2. Description of the Related Art
In Metal-Oxide-Semiconductor (MOS) device manufacturing, self-aligned metal silicide layers (also known as a "salicide" layers) are useful in reducing the sheet resistance of polysilicon interconnections, source regions and drains regions, as well as contact resistance. See, for example, Stanley Wolf et al., Silicon Processing for the VLSI Era I, 388-399 (Lattice Press 1986).
FIGS. 1-3 illustrate a conventional process for forming a metal salicide layer over a polysilicon gate, a source region and a drain region of an MOS transistor structure.
FIG. 1 illustrates a representative conventional MOS transistor structure 10. The MOS transistor structure 10 includes a thin gate oxide 12 overlying P-type silicon substrate 14 between N-type drain region 16 and N-type source region 18, both of which are formed in P-type silicon substrate 14. A polysilicon gate 20 overlies thin gate oxide 12, and field oxide regions 22 isolate MOS transistor structure 10 from neighboring device structures (not shown). Gate sidewall spacers 24, typically of silicon dioxide or silicon nitride, are formed on the sides of polysilicon gate 20 and thin gate oxide 12.
As illustrated in FIG. 2, in the first step of a conventional metal salicide formation process, a metal layer 28 is deposited over the surface of MOS transistor device 10. Metal layer 28 is conventionally deposited by a multi-directional evaporative or sputtering-based physical vapor deposition (PVD) process or a multi-directional chemical vapor deposition (CVD) process and is, therefore, of essentially equal thickness over the entire surface of MOS transistor structure 10.
Wherever metal layer 28 is in contact with silicon surfaces (i.e. source region 18, drain region 16 and the polysilicon surface of polysilicon gate 20) the metal is reacted to form a metal salicide layer. The conditions, such as temperature and gaseous ambient, employed for such a metal reaction are chosen to foster the reaction of the metal layer with these regions which have silicon surfaces while impeding reaction of the metal layer with the silicon dioxide or silicon nitride surfaces (i.e. the gate sidewall spacers and field oxide regions).
A selective etch is then used to remove unreacted metal from the surface of the gate sidewall spacers and field oxide regions, as well as any unreacted metal residue still remaining above the source region, drain region and polysilicon gate. The etch is "selective" since it does not remove the metal salicide layer that was formed on the surface of the silicon and polysilicon regions. The result, illustrated in FIG. 3, is a metal salicide layer 32 on the surface of drain region 16, a metal salicide layer 34 on the surface of source region 18 and a metal salicide layer 36 on the surface of polysilicon gate 20.
A drawback of conventional metal salicide processes is the tendency to form metal silicide "bridges" 40 between the salicide layer on source region 18, or drain region 16, and the salicide layer on the polysilicon gate, as shown in FIG. 4. Metal silicide bridges cause an undesirable electrical short between these regions.
Needed in the art is a process for forming a self-aligned metal silicide layer on an MOS transistor structure that provides a reduced susceptibility to the formation of metal silicide bridging defects.